The present invention generally relates to a LSI (Large Scale Integrated) circuit and more particularly to a bus driving system or circuit for a microprocessor.
In general, in the microprocessor, the data transfer among function blocks is effected via a bus or buses. FIG. 3A of the accompanying drawings shows, by way of example, a bus structure used heretofore and FIG. 3B shows a timing chart for illustrating operation of the same. In the following, operation of this bus structure will be reviewed briefly.
In the beginning, it must be pointed out that FIGS. 3A and 3B show only those components which are required for the operation involved in transmission of n-bit data DOUT-1, DOUT-2, . . . , DOUT-N (where n represents a positive integer) from a function block A to a function block B via bus wires as well as reception or detection of the data as data DIN-1, DIN-2, . . . , DIN-N in a function block B. Referring to the figures, n bus wires DB-1, DB-2, . . . , DB-n which constitute an n-bit bus are precharged to a supply voltage level VCC at a time point t0. When an activation signal EN is changed over to a high level VCC in the function block A at a time point t1, n-channel MOSFETs MN-i are turned on with the bus wires DB-i being switched to a low level 0V in case the bit signals DOUT-i (i=1, 2, . . . , n) are at the low level 0V. On the other hand, when the bit signals DOUT-i are at the high level VCC (supply voltage level), the n-channel MOSFETs MN-i are maintained in the non-conducting state (off-state) with the bus wires remaining at the high level VCC. Thus, n bit-signals DOUT-1, DOUT-2, . . . , DOUT-n make appearance at the n-bit bus wires DB-1, DB-2, . . . , DB-n, respectively. When a control signal CK for the function block B assumes the high level VCC at a time point t2, the signals on the bus wires DB-1, DB-2, . . . , DB-n are fetched by flip-flops FF-1, FF-2, . . . , FF-n, respectively, to be thus received as the data DIN-1, DIN-2, . . . , DIN-n, respectively. When the precharge signal PRE becomes high (VCC) at a time point t3, the bus wires DB-1, DB-2, DB-n are precharged, whereby the bus is set to the state ready for the succeeding operation cycle which is started at a time point t4. Parenthetically, the function block A and the function block B may be regarded as conventional logic blocks such as register files, execution logic units or the like.
The bus structure known heretofore suffers a problem that a large power is consumed for charge and discharge of wiring capacitances because voltages on a number of bus wires are caused swing to the full extent during each operation cycle.
For simplification of discussion, it is now assumed that the frequency at which the high level VCC are outputted to the bus wires is equal to that of the low level 0V. Then, in the hitherto known bus structure (FIG. 3A) which includes n bus wires DB-1, DB-2, . . . , DB-n (where n represents a positive integer), there makes appearance stochastically the low level 0V at the n/2 bus wires. The voltages at these n/2 bus wires are caused to make full swing from the high level VCC to the low level 0V and then to the high level VCC during one operation cycle, as can be seen from FIG. 3B. Refer to the signal waveform DOUT-i for the bus wire DB-i (FIG. 3B). In this manner, in the case of the bus driving circuit known heretofore, voltages of many bus wires (n/2 on an average) make full swing, which involves high power consumption due to charge and discharge of the wiring capacitances.
In the recent years, the performance of the microprocessor is increasingly enhanced. In reality, microprocessors having an internal bus of a large bit-width such as a 32-bit bus or a 64-bit bus is realized (e.g. refer to ISSCC DIGEST OF TECHNICAL PAPERS, pp. 106-107, February 1992). In the bus driving circuit for these high-performance microprocessors, the problem concerning the power consumption of the bus system becomes serious because the power consumption is in proportion to the bit-width (n) of the bus.
Another problem of the bus structure known heretofore can be seen in that signals on the neighboring bus wires are superposed on the inherent bus signal as the noise through the medium of inter-wire capacitances, thus giving rise to degradation of the noise margin and hence erroneous operation of the bus system. This problem will be elucidated below by reference to FIGS. 24A and 24B of the accompanying drawings.
Referring to FIG. 24A, switches S-1, S-2 and S-3 schematically represent the n-channel MOSFETs MN-1, MN-2 and MN-3, respectively, in the bus structure shown in FIG. 3A. It is assumed that the bus wires DB-1, DB-2 and DB-3 are physically juxtaposed in the order as illustrated. It is again assumed that the switches S-1 and S-3 are turned on with the switch S-2 being held in the off-state after the associated bus wires have been precharged. In that case, the signal on the bus wire DB-2 should intrinsically be held at the high level VCC. However, noise brought about when the signals on the neighboring bus wires DB-1 and DB-3 shift from the high level VCC to the low level 0V is superposed onto the signal of the bus wire DB-2 through the medium of the inter-wire capacitance. As a consequence, the potential on the bus wire DB-2 is pulled down to a level lower than the high level VCC. This crosstalk noise becomes more remarkable as the inter-wire capacitance of the bus increases, to thereby degrade the margin for noise (or noise margin). In an extreme case, the potential at the bus wire DB-2 may be pulled down to the level below a logical threshold value of the CMOS (Complementary metal-Oxide Semiconductor) circuit to be erroneously detected as the low-level signal.